FPGA 2012: Call for Papers

• FPGA Architecture: Novel logic block architectures, combination of FPGA fabric and system blocks (DSP, processors, memories, etc.), design of routing fabric, I/O interfaces, new commercial architectures and architectural features.
• FPGA Circuit Design: Novel FPGA circuits and circuit-level techniques, impact of process and design technologies, methods for analyzing and improving issues with soft-errors, leakage, static and dynamic power, clocking, power grid, yield, manufacturability, reliability, test; studies on future device technologies (e.g. nano-scale, 3D gate) for FPGAs.
• CAD for FPGAs: Placement, routing, re-timing, logic optimization, technology mapping, system-level partitioning, logic generators, testing and verification, CAD for FPGA-based accelerators, CAD for incremental FPGA design and on-line design mapping and optimization, CAD for modeling, analysis and optimization of timing and power.
• High-Level Abstractions and Tools for FPGAs: General-purpose and domain-specific models, languages, tools, and techniques to facilitate the design, development, debugging, verification, and deployment of large-scale and high-performance FPGA-based applications and systems - e.g. DSP, networking or embedded system tools and methodologies.
• FPGA-Based and FPGA-like computing engines: Compiled accelerators, reconfigurable computing, adaptive computing devices, systems and software, rapid-prototyping.
• Design Studies: Innovative uses of FPGA fabric for computation, exploitation of FPGA features and architectures, optimization of FPGA-based cores (e.g. arithmetic, DSP, security, embedded processors, memory interfaces, or other functions).
• Applications: Implementation of novel designs on FPGAs to achieve high-performance, low-power, or high-reliability, making use of the unique flexibility provided by FPGA architectures. Application-domain studies to analyze or improve FPGA architectures and implementations for networking, DSP, embedded, audio/video, automotive, imaging and other relevant areas.
• Panel Outlines: Topic proposals for the traditional Monday night Panel Session at FPGA.

FPGA uses a double-blind reviewing system. Manuscripts must not identify authors or their affiliations. Self-references should be shown as "Removed for blind review". Papers that identify authors will not be considered. Exceptions may be made for papers presenting new FPGA-related community infrastructure if the ability of reviewers to access that infrastructure is key to evaluating the paper. Please contact the Program Chair before submitting if you feel that it is not possible to avoid identifying paper authors.

Papers should be submitted on-line to: https://www.softconf.com/c/fpga2012

All papers should use the ACM formatting templates available at: http://www.acm.org/sigs/pubs/proceed/template.html

Notification of acceptance will be sent by mid-November. The authors of accepted papers will be required to submit the final camera-ready copy by early December. A proceedings of the accepted papers will be published by ACM and included in the Annual ACM/SIGDA CD-ROM Compendium publication.

Address questions about the technical program to:

Brad Hutchings, Program Chair FPGA 2012
Department of Electrical and Computer Engineering
Brigham Young University
Provo, UT 84602
hutch@ee.byu.edu

Address general questions about conference

Katherine Compton kati@engr.wisc.edu